The present invention disclosed herein relates to system-on-chips and more particularly, to a system-on-chip operable in a sleep mode with a retention input/output device.
A system-on-chip (hereinafter, referred to as ‘SOC’) is generally structured with an awake module (hereinafter, ‘power manager’) normally turned ON to control ON/OFF of power supplied each of a plurality of internal circuits, and an input/output device for interfacing with external devices out of the SOC.
If the SOC is in a sleep mode, most internal circuits are powered OFF by the power manager. But, external devices coupled to the input/output device of the SOC can not be turned OFF. Thus the input/output device coupled to the external devices is required to maintain its turn-ON state for interface with the external devices and holding a specific value (hereinafter, referred to as ‘sleep value’). The sleep value means a signal of constant low or high level for preventing a leakage current from flowing through the input/output device in the sleep mode of the SOC. Hereinafter, the sleep value is considered to be at a low level in general.
The SOC usually needs an additional device for maintaining such a sleep value. The power manager of the SOC includes a register for storing a sleep value and the input/output device includes the awake multiplexer for selecting the sleep value.
FIG. 1 is a circuit diagram of an awake multiplexer employed in a general input/output device.
Referring to FIG. 1, the awake multiplexer employed in the input/output device includes two AND gates AND1 and AND2, an OR gate OR1, and an inverter INV1.
When an SOC is in a normal mode, a control signal PWRDN goes to a low level. The control signal PWRDN having a low level is applied to a second input node of the AND gate AND2. The control signal PWRDN is also inverted to a high level through the inverter INV1. The control signal PWRDN inverted into high level is applied to a second input node of the AND gate AND1. As the AND gate AND2 receives the low level signal at its second input node, it always outputs a low level signal to a second input node of the OR gate OR1 regardless of a value of an input signal A12 corresponding to a sleep value applied to its first input node. As the AND gate AND1 receives the high level signal at its second input node, it outputs a high or low level signal to a first input node of the OR gate OR1 in response to a level (high or low) of an input signal A11 corresponding to a normal value applied to its first input node. Thus, the OR gate OR1 receives the input signal A11 at its first input node and the low level signal at its second input node. As a result, the OR gate OR1 outputs a level of the input signal A11. Thus, the awake multiplexer selectively outputs the input signal A11 when the SOC is in the normal mode and the control signal PWRDN is at a low level.
When the SOC is in a sleep mode, the control signal PWRDN goes to a high level. The control signal PWRDN having a high level makes the awake multiplexer select and output the input signal A12. An operation of the awake multiplexer in the sleep mode of the SOC is reverse of that of the normal mode of the SOC, so will not be further detailed.
In the sleep mode of the SOC, a circuit transferring the input signal A11 is turned OFF. Thus, the first input of the AND gate AND1 of the awake multiplexer is transitioned into a floating state without any further input of the signal A11 corresponding to the normal mode. This floating state is prevented by the AND gate AND1 of the awake multiplexer.
FIG. 2 is a circuit diagram of the AND gate shown in FIG. 1.
Referring to FIG. 2, the AND gates, AND1 and AND2, shown in FIG. 1 each includes PMOS transistors MP21 and MP22, NMOS transistors MN21 and MN22, and an inverter INV2. The AND gates AND1 and AND2 are the same in structure, so the description of AND gate AND1 in FIG. 2 applies also AND gate AND2. AND gate AND1 is merely used as an example in FIG. 2.
Sources of the PMOS transistors MP21 and MP22 are connected to an operation voltage VDD in common. A gate of the PMOS transistor MP21 is coupled to the input signal A11 and connected to a gate of the NMOS transistor MN21. A drain of the PMOS transistor MP21 is connected to a drain of the NMOS transistor MN21. An output node of the inverter INV2 is an output node OUT of the AND gate AND1. The input signal A11 is applied to the first input node of the AND gate AND1 and the control signal PWRDN is applied to the second input node of the AND gate AND1.
A gate of the PMOS transistor MP22 is coupled to the control signal PWRDN. A drain of the PMOS transistor MP22 is connected to the drain of the NMOS transistor MN21. A source of the NMOS transistor MN21 is connected to a drain of the NMOS transistor MN22. A gate of the NMOS transistor MN22 is coupled to the control signal PWRDN. A source of the NMOS transistor MN22 is connected to a ground GND.
When the SOC is in the normal mode, the control signal PWRDN becomes at a low level. The control signal PWRDN of low level is inverted into a high level. The control signal PWRDN inverted into a high level turns the NMOS transistor MN22 of the AND gate AND1 ON and turns the PMOS transistor MP22 OFF. During this, if the input signal A11 is at a high level, the PMOS transistor MP21 is turned OFF while the NMOS transistor MN21 is turned ON. Thus, a current through the NMOS transistors MN21 and MN22 flows into the ground GND and a voltage of a node N21 falls down to a low level. This low level voltage is converted into and output as a high level signal through the inverter INV2. If the input signal A11 is at a low level, the AND gate AND1 outputs a low level signal. An operation with the input signal A11 of low level is reverse of that when the input signal A11 is at a high level, so will not be further detailed. Thus, in the normal mode of the SOC, the awake multiplexer selects and outputs the input signal A11 in correspondence with the normal value when the control signal PWRDN is at a low level.
Referring to the description relevant to FIG. 1, when the SOC is in the sleep mode, the control signal PWRDN is high level. The control signal PWRDN of a high level enables the awake multiplexer to select and output the signal A12 corresponding to the sleep value. After outputting the signal A12, a circuit transferring the input signal A11 is turned OFF because the SOC is in the sleep mode. Thus, the first input node of the AND gate AND1 of the awake multiplexer is floated when receiving the input signal A11 corresponding to the normal mode. But the AND gate AND1 receives the inverted control signal /PWRDN of a low level through the inverter INV1 and then the NMOS transistor MN22 is transitioned into an open state to the ground GND by the inverted control signal /PWRDN having a low level. Further, the PMOS transistor MP22 is turned ON to hold the node N21 at a high level. The high level signal of the node N21 is inverted into a low level signal through the inverter INV2. As an output of the AND gate AND1 maintains the low level signal regardless of a state of the input signal A11, the awake multiplexer is able to interrupt a leakage current from preventing a floating state.
The SOC includes at least one or more buffers for transferring a sleep value to the awake multiplexer of the input/output device from a register of the power manager. The sleep value stored in the register of the power manager is transferred to the awake multiplexer of the input/output device through the buffer. The register of the power manager and the awake multiplexer of the input/output device need to be continuously supplied with power in order to maintain a sleep value during the sleep mode of the SOC. Therefore, the awake multiplexer is included in the input/output device for maintaining an ON-state even during the sleep mode, and supplied with power.
The input/output device includes a plurality of input/output cells, and the awake multiplexer is usually placed at a front of the input/output cell. Thus, as the number of the input/output cells gets larger, the number of the awake multiplexers used in the input/output device increases to enlarge a size of the input/output device. If the input/output device is enlarged in size, a rate of power consumption by the input/output device becomes higher. increasing an amount of leakage current therein. With the larger number of the awake multiplexers of the input/output device, the number of the buffers for connecting the registers of the power manager to the awake multiplexers of the input/output device is also increased. Because there are so many buffers, an amount of leakage current further increases accordingly. Additionally, the power manager is enlarged in size by including the register for storing a sleep value, so that a rate of power consumption becomes higher, and there is a corresponding increase in leakage current.
Therefore, the SOC including such a general input/output device is disadvantageous to power consumption and leakage current because it causes a real extension of a circuit supplying power for holding a specific value in the sleep mode.